1. Field of the Invention
This invention relates generally to the design of phase locked loops. More particularly, it relates to a digital phase locked loop having improved acquisition and jitter characteristics, and/or having a high-current, high-precision charge pump.
2. Background of Related Art
A conventional digital phase locked loop (PLL) 100 as shown in FIG. 1 comprises two main components: a digital phase detector 102 and a controlled oscillator 104.
In FIG. 1, a digital phase detector 102 receives both a reference frequency signal f.sub.REF and a variable frequency signal f.sub.VAR. The reference frequency signal f.sub.REF is, e.g., an output of a highly accurate crystal oscillator. The variable frequency signal f.sub.VAR is typically the output frequency, or the output frequency divided by a frequency divider 106 to provide a slower rate clock signal, allowing the use of a slower rate crystal oscillator or other clock source as the reference frequency signal f.sub.REF.
The digital phase detector 102 compares the phase of the reference frequency signal f.sub.REF with that of the variable frequency signal f.sub.VAR to determine whether or not the relative phase and frequency of the output signal f.sub.OUT of the PLL 100 is higher or lower than expected.
If the output frequency signal f.sub.OUT is too high as compared to the reference frequency signal f.sub.REF, the digital phase detector 102 activates a slow down signal DN to the controlled oscillator 104 to slow down the frequency and/or shift the phase of the output frequency signal f.sub.OUT of the PLL 100. If, on the other hand, the output frequency and/or phase of the output frequency signal F.sub.OUT is too low, the digital phase detector 102 provides a speed up signal UP to the controlled oscillator 104 to speed up the frequency and/or shift the phase of the output frequency signal f.sub.OUT of the PLL 100. Thus, the controlled oscillator 104 adjusts its output frequency signal f.sub.OUT in accordance with UP/DN controls provided by the digital phase detector 102.
Many mechanisms can be used to provide the adjustment in the frequency and/or phase of the output frequency signal F.sub.OUT. For instance, a popular mechanism is the use of a charge pump and a loop filter to transform the UP/DN pulse controls from the digital phase detector 102 into a voltage charged on a capacitor, which then controls the frequency of a voltage controlled oscillator (VCO) in the controlled oscillator 104.
With digital PLLs, instruction signals from the digital phase detector 102 to the digitally controlled oscillator 104 have only two basic modes, i.e., UP and DN (and a third mode of neither up or down, typically represented by the simultaneous activation of both the UP and DN signals). The width of the UP and DN control signal pulses to the controlled oscillator 104 are varied based on the phase difference between the reference frequency signal F.sub.REF and the variable frequency f.sub.VAR. Among other factors, resolution in the width of the UP and DN control signal pulses results in a given amount of jitter and requires a given amount of acquisition time to lock phases. Thus, the resolution of the pulse width of both the UP and DN control signals is minimized, but nevertheless has a finite, digitally derived width limited by the speed of the digital logic for activating and deactivating the UP and DN control signal pulses.
Thus, when the PLL 100 is locked, the digital phase detector 102 will activate both the UP and DN signals each having a minimum pulse width. Then, if the output frequency signal f.sub.OUT as determined by a comparison of the variable frequency signal F.sub.VAR to the reference frequency signal f.sub.REF falls behind, the digital phase detector 102 will widen the activation pulse of the UP control signal to have an appropriately larger width than the DN control signal. On the other hand, if the output frequency signal F.sub.OUT becomes ahead in phase as determined by a comparison of the variable frequency signal F.sub.VAR to the reference frequency signal F.sub.REF, then the digital phase detector 102 will widen the activation pulse of the DN control signal to be wider than the activation pulse of the UP control signal, which may be at a minimum pulse width.
Unfortunately, the jitter and/or acquisition time characteristics of a conventional digital phase locked loop are related to the resolution of the control signals from a phase detector to a digitally controlled oscillator. As requirements for more stable clock signals derived from digital phase locked loops continue to tighten, there has become a need for more accurate control of a digital phase locked loop to provide improved jitter and/or acquisition time characteristics over conventional digital phase locked loop devices.